I. Field
The present disclosure relates generally to circuits, and more specifically to a phase-locked loop.
II. Background
Phase-locked loops (PLLs) are commonly used in many electronics circuits and are particularly important in communication circuits. For example, digital systems use clock signals to trigger synchronous circuits, e.g., flip-flops. Transmitter and receiver systems use local oscillator (LO) signals for frequency upconversion and downconversion, respectively. Wireless devices (e.g., cellular phones) in wireless communication systems typically use clock signals for digital circuitry and LO signals for transmitter and receiver circuitry. Clock and LO signals are often generated with voltage-controlled oscillators (VCOs) operating within PLLs.
A PLL typically includes a phase frequency detector, a charge pump, a loop filter, and a VCO. The phase frequency detector, charge pump, loop filter collectively detect phase error between a reference signal and a clock signal derived from the VCO and generate a control signal for the VCO. The control signal adjusts the frequency of the VCO such that the clock signal is locked to the reference signal.
The phase frequency detector typically generates a pair of signals that is commonly referred to as up and down signals. One signal is typically turned on longer in each clock cycle depending on whether the clock signal is early or late relative to the reference signal. The up and down signals are used to couple current sources within the charge pump to the output. Ideally, the phase frequency detector and charge pump should have a linear transfer function of output charge versus phase error. However, due to mismatch of circuits used for the charge pump, this linear transfer function is typically not achieved. Consequently, the output change from the up signal is often not equal to the output charge from the down signal for phase errors of the same magnitude but opposite polarity. This charge error is due to up/down current mismatch in the charge pump, which may result from transistor device mismatch and other factors. Non-linearity of the charge pump due to current mismatch may cause additional phase noise that may degrade performance.
There is therefore a need in the art for a phase frequency detector and a charge pump that can provide good performance for a PLL.